1. Field of the Invention
The invention relates generally to the field of stacked integrated circuits.
More specifically, the invention relates to using conductive stud bumps while processing bare integrated circuit die during neolayer lamination and potting for use in fabricating a stackable layer comprising one or more integrated circuit chips.
2. Description of the Related Art
The ability to fabricate very thin, stackable layers containing one or a plurality of homogeneous or heterogeneous integrated circuit chips is desirable and allows high density, high speed electronic systems to be assembled for use in military, space, security and other applications.
Examples of such layers and modules are disclosed in U.S. Pat. No. 6,072,234, Stack of Equal Layer Neo-Chips Containing Encapsulated IC Chips of Different Sizes; U.S. Pat. No. 6,797,537, Method of Making Stackable Layers Containing Encapsulated Integrated Circuit Chips With One or More Overlying Interconnect Layers; U.S. Pat. No. 6,784,547, Stackable Layers Containing Encapsulated Integrated Circuit Chips With One or More Overlying Interconnect Layers; U.S. Pat. No. 6,117,704, Stackable Layer Containing Encapsulated Chips; U.S. Pat. No. 5,953,588; Stackable Layers Containing Encapsulated IC Chips; and U.S. Pat. No. 7,768,113, Stackable Tier Structure Comprising Prefabricated High Density Feed-through.
The stacking and interconnection of very thin microelectronic layers permits high circuit speeds in part because of short lead lengths with related reduced parasitic impedance and reduced electron time-of-flight. These desirable features combined with a very high number of circuit and layer interconnections allow relatively large I/O designs to be implemented in a small volume.
The present invention provides a stackable integrated circuit chip (which integrated circuit chip is also herein referred to as an “IC” or “die”) for use in multi-layer, microelectronic modules such as are disclosed in the above referenced patents. The use of potted and thinned stacked layers having rerouted die therein permits die having different functions, and therefore different areas, to be stacked as if they were same size die.
A prior art process for making a “neo-chip” or “neo-layer” involves the “potting” of individual IC chips in a encapsulant or compound which supports and insulates each chip and which can be cut or diced to provide equal area layers so that chips having different sizes can be stacked as layers whose edges are coplanar with one another. The individual chips, in die form, may be incorporated into neo-wafer form for processing. Thereafter, layers are cut out of the neo-wafer and incorporated into stacks.
The prior art neo-layer processes may include the processing and stacking of chips purchased as individual die. Beneficially, chips purchased as individual die are generally “known good” die which have been “burned in” and are therefore pre-tested prior to stacking.
Prior to stacking, one or more known good die are used to create the “neo” wafer by locating those known good die in a potting fixture. Potting material is flowed into the fixture, which is enclosed and then the potting material is cured. The resulting “neo-wafer” is removed from the fixture and then subjected to pre-stacking process steps including spinning on a layer of dielectric material, forming vias through the dielectric material to reach the terminals on the die in the wafer, and then forming electrical conductors in the form of metal traces that lead from the die terminals on the surface of the dielectric layer or layers. Thereafter the neo-wafer is diced into one or more layers suitable for stacking, each layer containing at least one known good die.
Each layer of a completed stack has electrical leads in the form of conductive metal traces used to connect the IC circuitry of the embedded chip (or chips) to one or more access planes, where the traces are available for connection to exterior circuitry.
Major cost-saving benefits can be obtained by the sole use of “known good” die, and the use/of a neo-wafer in processing one or more of such die.
Neo-stacking offers significant improvements over silicon bare die stacking, but it also proved troublesome under certain market circumstances. In particular, it is often difficult to buy bare die because many manufacturers will only sell packaged die.
For instance, when trying to buy bare DRAM die from a particular manufacturer, it was discovered that the manufacturer would not sell bare DRAM die, but would sell the DRAM die already pre-tested and installed in prepackaged integrated circuit packages.
Because of the demand for die and the high capital investment necessary to be a mass manufacturer of them, it is difficult to induce a mass fabricator of die to supply only die as opposed to the usual finished product which is a packaged or encapsulated integrated circuit chip. Such mass fabricators are typically fully occupied with the manufacture of finished and packaged integrated circuits. Individual IC chips are not typically offered for sale either in wafer or in die form.
Even in those cases where a mass fabricator can be induced to manufacture and sell a bare functional die, the die may be delivered in wafers or diced without testing. In other words, a die is normally tested after it is connected to its lead frame and packaged on a lead frame or in an encapsulant to ascertain whether it is operable as intended. Mass testing of bare die is not a procedure that many mass fabricators are equipped or even inclined to do. Therefore, a purchaser of bare die must test each die individually in order to determine its operability or the yield. Bare die testing is too limited to ensure acceptable yields, while comprehensive testing and burn-in renders bare die production cost-ineffective. These problems are sometimes referred to as the “known good die” or “KGD” problem.
Because prepackaged die are burned in and therefore contain known good die, it is desirable to depackage the known good die within a prepackaged IC package for use in certain applications such as for use in the above neo-processes.
Unfortunately, for both die obtained as bare die and depackaged die, during the processing steps of neowafer fabrication, certain elements of the bare die, particularly the aluminum contact pads, are prone to corrosion caused by chemicals used during lithography or elsewhere in the process; particularly corrosion on the side aluminum walls of the IC contact pads when nickel and palladium are present on the surface of the aluminum contact pads.
Additionally, some circuit elements on the bare die that are used in the neolayer process are sensitive to the radiation used in certain process steps and can be damaged by exposure thereto.
What is needed is a neolayer fabrication method that protects the aluminum IC pads from corrosion and any active IC circuit elements from radiation during processing and that provides a neolayer for use as a stackable layer in a multi-layer electronic module.